This invention relates to a method for manufacturing polycrystalline silicon having high resistance.
The polycrystalline silicon having high resistance is widely used as a material for semiconductor devices and in particular for static random access memories (SRAM). FIG. 1 illustrates a cell structure of SRAM that is currently in wide use, in which two high resistors (R1 and R2) and MOS transistors (T1 and T2) in series are coupled between a source supply voltage Vcc and a ground potential Vss. Nodes (1) and (2) between the high resistors and the MOS transistors are respectively coupled to gates of the MOS transistors (T2) and (T1) in a cross connection. Between these node points (1), (2) and bit lines (BL) (BL) are respectively connected, MOS transistors T3 and T4, gates of which are coupled to word line (WL). In an alternative embodiment, ions of inert gases, rather than nitrogen ions, are implanted into polycrystalline silicon layer 15.
For the SRAM, the polycrystalline silicon normally having a resistance of 200-300 G.OMEGA. is used. With the polycrystalline silicon, information charged at the node points (1), (2) makes it possible to supplement leakage current leaked out to the transistors (T1, T2, T3 and T4). The higher the integration of memory devices becomes, the more the polycrystalline silicon having higher resistance than 200-300 G.OMEGA. is needed.
Many researches have been made these days to methods for manufacturing polycrystalline silicon having high resistance. In the prior art, the high resistance in the polycrystalline silicon has been achieved through reducing thickness of the polycrystalline silicon or implanting such impurities as arsenic (As), phosphorus (P) and boron (B) with a 10.sup.11 -10.sup.14 /cm.sup.2 dose. Although the resistance of polycrystalline silicon could be increased when the above mentioned methods are employed, there arise complexities in process conditions or specific limitations in increasing the resistance to be required in higher density SRAM.